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- 1 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b 18mb qdrii sram specification 165fbga with pb & pb-free (rohs compliant) * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or simi- lar applications where product failure could result in lo ss of life or personal or ph ysical harm, or any military or defense application, or any governmental procuremen t to which special terms or provisions may apply.
- 2 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b document title 512kx36-bit,1mx18-bit qdr tm ii b4 sram the attached data sheets are prepared and approved by samsung el ectronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to yo ur requests and questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or contact headquarters. revision history rev. no. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.0 2.0 3.0 4.0 5.0 remark advance preliminary preliminary preliminary preliminary preliminary preliminary preliminary final final final final final history 1. initial document. 1. change the boundary scan exit order. 2. correct the overshoot and undershoot timing diagram. 1. change jtag block diagram 1. add the speed bin (-25) 1. correct the jtag id register definition 2. correct the ac timing parameter (delete the tkhk h max value) 1. change the maximum clock cycle time. 2. correct the 165fbga package ball size. 1. add the power up/down sequencing comment. 2. update the dc current parameter (icc and isb). 3. change the max. speed bin from -33 to -30. 1. change the isb1. 1. final spec release 1. delete the x8 org. 2. delete the 300mhz speed bin 1. add the industrial temp. & lead free package 1. add the 300mhz speed bin 1. change vss/sa to nc/sa in pin configuration speed bin from to -30 200 230 -25 180 210 -20 160 190 -16 140 170 draft date oct. 17. 2002 dec. 16, 2002 dec. 26, 2002 jan. 27, 2003 mar. 20, 2003 april. 4, 2003 june. 20, 2003 oct. 20. 2003 oct. 31, 2003 nov. 28, 2003 nov. 10. 2004 mar. 29. 2006 jul. 26 2006
- 3 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b 36 (or 18) q(data out) (echo clock out) cq, cq 72 512kx36-bit, 1mx18-bit qdr tm ii b4 sram features functional block diagram ? 1.8v+0.1v/-0.1v power supply. ? dll circuitry for wide output data valid window and future fre- quency scaling. ? i/o supply voltage 1.5v+0.1v/-0.1v for 1.5v i/o, 1.8v+0.1v/-0.1v for 1.8v i/o . ? separate independent read and write data ports with concurrent read and write operation ? hstl i/o ? full data coherency, providing most current data. ? synchronous pipeline read with self timed late write. ? registered address, control and data input/output. ? ddr (double data rate) interface on read and write ports. ? fixed 4-bit burst for both read and write operation. ? clock-stop supports to reduce current. ? two input clocks (k and k ) for accurate ddr timing at clock rising edges only. ? two input clocks for output data (c and c ) to minimize clock-skew and flight-time mismatches. ? two echo clocks (cq and cq ) to enhance output data traceability. ? single address bus. ? byte write (x18, x36) function. ? separate read/write control pin(r and w ) ? simple depth expansion with no data contention. ? programmable output impedance. ? jtag 1149.1 compatible test access port. ? 165fbga(11x15 ball array) with body size of 13mmx15mm. & lead free ? operating in commercial and industrial temperature range. r address w c c d(data in) add reg data reg clk gen ctrl logic 512kx36 (1mx18) memory array write driver k k bw x 36 (or 18) select output control sense amps write/read decode output reg output select output driver notes : 1. numbers in ( ) are for x18 device 72 17 17 (or 18) 4 (or 2) 72(or 36) 72(or 36) 144 * -e(f)c(i) e(f) [package type] : e-pb free, f-pb c(i) [operating temperature] : c-commercial, i-industrial organization part number cycle time access time unit x36 k7r163684b-e(f)c(i)30 3.3 0.45 ns k7r163684b-e(f)c(i)25 4.0 0.45 ns k7r163684b-e(f)c(i)20 5.0 0.45 ns k7r163684b-e(f)c(i)16 6.0 0.50 ns x18 k7r161884b-e(f)c(i)30 3.3 0.45 ns k7r161884b-e(f)c(i)25 4.0 0.45 ns k7r161884b-e(f)c(i)20 5.0 0.45 ns k7r161884b-e(f)c(i)16 6.0 0.50 ns qdr sram and quad data rate comprise a new family of products dev eloped by cypress, hitachi, idt, micron, nec and samsung techn ology. (or 18) (or 36) (or 36) (or 72)
- 4 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b pin configurations (top view) k7r163684b(512kx36) notes : 1. * checked no connect (nc) pins are reserved for higher density address, i.e. 9a for 32mb, 3a for 72mb, 10a for 144mb an d 2a for 288mb. 2. bw 0 controls write to d0:d8, bw 1 controls write to d9:d17, bw 2 controls write to d18:d26 and bw 3 controls write to d27:d35. 1 2 3 4 5 6 7 8 9 10 11 a cq nc/sa* nc/sa* w bw 2 k bw 1 r nc/sa* nc/sa* cq b q27 q18 d18 sa bw 3 kbw 0 sa d17 q17 q8 c d27 q28 d19 v ss sa nc sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa c sa sa q9 d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi pin name notes: 1. c, c, k or k cannot be set to v ref voltage. 2. when zq pin is directly connected to v dd output impedance is set to minimum value and it cannot be connected to ground or left unconnected . 3. not connected to chip pad internally. symbol pin numbers description note k, k 6b, 6a input clock c, c 6p, 6r input clock for output data 1 cq, cq 11a, 1a output echo clock doff 1h dll disable when low sa 4b,8b,5c,7c,5n-7n,4p,5p,7p,8p,3r-5r,7r-9r address inputs d0-35 10p,11n,11m,10k,11j,11g,10e,11d,11c,10n,9m,9l 9j,10g,9f,10d,9c,9b,3b,3c,2d,3f,2g,3j,3l,3m,2n 1c,1d,2e,1g,1j,2k,1m,1n,2p data inputs q0-35 11p,10m,11l,11k,10j,11f,11e,10c,11b,9p,9n,10l 9k,9g,10f,9e,9d,10b,2b,3d,3e,2f,3g,3k,2l,3n 3p,1b,2c,1e,1f,2j,1k,1l,2m,1p data outputs w 4a write control pin, active when low r 8a read control pin, active when low bw 0 , bw 1, bw 2 , bw 3 7b,7a,5a,5b block write control pin, active when low v ref 2h,10h input reference voltage zq 11h output driver impedance control input 2 v dd 5f,7f,5g,7g,5h,7h,5j,7j,5k,7k power supply (1.8 v) v ddq 4e,8e,4f,8f,4g,8g,3h,4h,8h,9h,4j,8j,4k,8k,4l,8l output power supply (1.5v or 1.8v) v ss 4c,8c,4d-8d,5e-7e,6f,6g,6h,6j,6k,5l-7l,4m, 8m,4n,8n ground tms 10r jtag test mode select tdi 11r jtag test data input tck 2r jtag test clock tdo 1r jtag test data output nc 2a,3a,10a,6c,9a no connect 3
- 5 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b pin configurations (top view) k7r161884b(1mx18) notes: 1. * checked no connect (nc) pins are reserved for higher density address, i.e. 3a for 36mb, 10a for 72mb and 2a for 144mb. 2. bw 0 controls write to d0:d8 and bw 1 controls write to d9:d17. 1 2 3 4 5 6 7 8 9 10 11 a cq nc/sa* nc/sa* w bw 1 k nc r sa nc/sa* cq b nc q9 d9 sa nc k bw 0 sa nc nc q8 c nc nc d10 v ss sa nc sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi pin name notes: 1. c, c, k or k cannot be set to v ref voltage. 2. when zq pin is directly connected to v dd output impedance is set to minimum value and it cannot be connected to ground or left unconnected . 3. not connected to chip pad internally. symbol pin numbers description note k, k 6b, 6a input clock c, c 6p, 6r input clock for output data 1 cq, cq 11a, 1a output echo clock doff 1h dll disable when low sa 9a,4b,8b,5c,7c,5n-7n,4p,5p,7p,8p,3r-5r,7r-9r address inputs d0-17 10p,11n,11m,10k,11j,11g,10e,11d,11c,3b,3c,2d 3f,2g,3j,3l,3m,2n data inputs q0-17 11p,10m,11l,11k,10j,11f,11e,10c,11b,2b,3d,3e 2f,3g,3k,2l,3n,3p data outputs w 4a write control pin, active when low r 8a read control pin, active when low bw 0 , bw 1 7b, 5a block write control pin, active when low v ref 2h,10h input reference voltage zq 11h output driver impedance control input 2 v dd 5f,7f,5g,7g,5h,7h,5j,7j,5k,7k power supply (1.8 v) v ddq 4e,8e,4f,8f,4g,8g,3h,4h,8h,9h,4j,8j,4k,8k,4l,8l output power supply (1.5v or 1.8v) v ss 4c,8c,4d-8d,5e-7e,6f,6g,6h,6j,6k,5l-7l,4m-8m,4n,8n ground tms 10r jtag test mode select tdi 11r jtag test data input tck 2r jtag test clock tdo 1r jtag test data output nc 2a,3a,10a,7a,1b,5b,9b,10b,1c,2c,6c,9c,1d,9d,10d,1e,2e,9e, 1f,9f,10f,1g,9g,10g,1j,2j,9j,1k,2k,9k,1l,9l,10l,1m 2m,9m,1n,9n,10n,1p,2p,9p no connect 3
- 6 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b the k7r163684b and k7r161884b are 18,874,368-bits qdr (quad data rate) synchronous pipelined burst srams. they are organized as 524,288 words by 36bits for k7r163684b and 1,048,576 words by 18 bits for k7r161884b. the qdr operation is possible by supporting ddr read and writ e operations through separate data output and input ports with the same cycle. memory bandwidth is maximized as data can be transferred into sram on every rising edge of k and k , and transferred out of sram on every rising edge of c and c . and totally independent read and write ports eliminate the need for high speed bus turn around. address for read and write are latched on alternate rising edges of the input clock k. data inputs, and all control signals are sy nchronized to the input clock (k or k ). normally data outputs are synchronized to output clocks (c and c ), but when c and c are tied high, the data outputs are synchronized to the input clocks (k and k ). read data are referenced to echo clock (cq or cq ) outputs. common address bus is used to access address both for read and write operations. the internal burst counter is fixed to 4-bit sequential for bot h read and write operations, requiring tow full clock bus cycles . any request that attempts to interrupt a burst operation in progress is ignored. synchronous pipeline read and late write enable high speed operations. simple depth expansion is accomplished by using r and w for port selection. byte write operation is supported with bw 0 and bw 1 (bw 2 and bw 3) pins. nibble write operation is supported with nw 0 and nw 1 pins for x8 device. ieee 1149.1 serial boundary scan (jtag) simplifies monitoring package pads attachment status with system. the k7r163684b and k7r161884b are implemented with samsung's high performance 6t cmos technology and is available in 165pin fbga packages. multip le power and ground pins minimize ground bounce. general description read operations read cycles are init iated by activating r at the rising edge of the positive input clock k. address is presented and stored in the read address register sync hronized with k clock. for 4-bit burst ddr operation, it will access four 36-bit or 18-bit or 8-bit data words with each read command. the first pipelined data is transferr ed out of the device triggered by c clock following next k clock rising edge. next burst data is triggered by the rising edge of following c clock rising edge. the process continues until all four data are transferred. continuous read operations are initiated with k clock rising edge. and pipelined data are transferred out of device on every rising edge of both c and c clocks. in case c and c tied to high, output data are triggered by k and k instead of c and c . when the r is disabled after a read operation, the k7r163684b and k7r161884b will first complete burst read operation before entering into deselect mode at the next k clock rising edge. then output drivers disabled autom atically to high impedance state. echo clock operation to assure the output traceability, the sram provides t he output echo clock, pair of compliment clock cq and cq , which are synchronized with internal data output. echo clocks run free during normal operation. the echo clock is triggered by internal output clock si gnal, and transferred to external through same structures as output driver.
- 7 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b write cycles are initiated by activating w at the rising edge of the positive input clock k. address is presented and stored in the write addr ess register synchroni zed with k clock. for 4-bit burst ddr operation, it will write four 36-bi t or 18-bit or 8-bit data words with each write command. the first ?late? data is transferred and registered in to the device synchronous wi th next k clock rising edge. next burst data is transferred and regi stered synchronous with following k clock rising edge. the process continues until all four data are transferred and registered. continuous write operations are initiated with k rising edge. and ?late writed? data is presented to the device on every rising edge of both k and k clocks. the device disregards input data presented on the same cycle w disabled. when the w is disabled after a read operation, the k7 r163684b and k7r161884b will first complete burst read operation before entering into des elect mode at the next k clock rising edge. the k7r163684b and k7r161884b support byte write operations. with activating bw 0 or bw 1 (bw 2 or bw 3) in write cycle, only one byte of input data is presented. in k7r161884b, bw 0 controls write operation to d0:d8, bw 1 controls write operation to d9:d17. and in k7r163684b bw 2 controls write operation to d18:d26, bw 3 controls write operation to d27:d35. write operations depth expansion the k7r163684b and k7r161884b can be operated with the single clock pair k and k , instead of c or c for output clocks. to operate these devices in single clock mode, c and c must be tied high during power up and must be maintained high during operation. after power up, this device can?t change to or from single clock mode. system flight time and clock skew could not be compensated in this mode. separate input and output ports enables easy depth expansion. each port can be selected and deselected independently and read and write operation do not affect each other. before chip deselected, all read and wr ite pending operations are completed. the designer can program the sram's output buffe r impedance by terminating the zq pin to v ss through a precision resistor (rq). the value of rq (within 15%) is five times the output impedance desired. for example, 250 ? resistor will give an output impedance of 50 ? . impedance updates occur early in cycles that do not ac tivate the outputs, such as deselect cycles. in all cases impedance updates are transparent to t he user and do not produce access time ?push-outs? or other anomalous behavior in the sram. there are no power up requirements for the sram. however, to guarantee optimum output driver impedance after power up, the sram needs 1024 non-read cycles. single clock mode programmable impedance output buffer operation the following power-up supply voltage application is recommended: v ss , v dd , v ddq , v ref , then v in . v dd and v ddq can be applied simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-up. the following power-down supply voltage removal sequence is recommended: v in , v ref , v ddq , v dd , v ss . v dd and v ddq can be removed simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-down. power-up/power-down supply voltage sequencing
- 8 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b state diagram notes : 1. internal burst counter is fixed as 2-bit linear, i.e. when first address is a0+0, next internal burst address is a0+1. 2. ?read? refers to read active status with r =low, ?read ? refers to read inactive status with r =high. ?write? and "write " are the same case. 3. read and write state machine can be active simultaneously. 4. state machine control timing sequence is controlled by k. read ddr read d count=d count+1 power-up write nop load new read address d count=0 always write always read write read d count=2 increment read address read nop increment write address ddr write d count=d count+1 load new write address d count=0 always read d count=1 read d count=2 always write d count=2 write d count=1 write d count=2
- 9 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b write truth table (x18) notes: 1. x means ?don t care?. 2. all inputs in this table must meet setup and hold time around the rising edge of input clock k or k ( ). 3. assumes a write cycle was initiated. 4. this table illustrates operation for x18 devices. k k bw 0 bw 1 operation l l write all bytes ( k ) l l write all bytes ( k ) l h write byte 0 ( k ) l h write byte 0 ( k ) h l write byte 1 ( k ) h l write byte 1 ( k ) h h write nothing ( k ) h h write nothing ( k ) write truth table (x36) notes: 1. x means ?don t care?. 2. all inputs in this table must meet setup and hold time around the rising edge of input clock k or k ( ). 3. assumes a write cycle was initiated. k k bw 0 bw 1 bw 2 bw 3 operation llll write all bytes ( k ) llll write all bytes ( k ) l h h h write byte 0 ( k ) l h h h write byte 0 ( k ) h l h h write byte 1 ( k ) h l h h write byte 1 ( k ) h h l l write byte 2 and byte 3 ( k ) h h l l write byte 2 and byte 3 ( k ) hhhh write nothing ( k ) hhhh write nothing ( k ) truth tables synchronous truth table notes: 1. x means ?don t care?. 2. the rising edge of clock is symbolized by ( ). 3. before enter into clock stop status, all pending read and write operations will be completed. 4. this signal was high on previous k clock rising edge. initiating consecutive read or write operations on consecu tive k clock rising edges is not permitted. the device will ignore the second request. 5. if this signal was low to in itiated the previous cycle, this signal becomes a don t care for this operation however it is strongly recommended that this signal is brought high as shown in the truth table. k r w d q operation d(a1) d(a2) d(a3) d(a4) q(a1) q(a2) q(a3) q(a4) stopped x x previous state previous state previous state previous state previous state previous state previous state previous state clock stop h h x x x x high-z high-z high-z high-z no operation l 4 xx x x x d out at c (t+1) d out at c(t+2) d out at c (t+2) d out at c(t+3) read h 5 l 4 din at k(t+1) din at k (t+1) din at k(t+2) din at k (t+2) xxxxwrite
- 10 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b dc electrical characteristics (v dd =1.8v 0.1v, t a =0 c to +70 c) notes: 1. minimum cycle. i out =0ma. 2. |i oh |=(v ddq /2)/(rq/5) 15% for 175 ? rq 350 ? . 3. |i ol |=(v ddq /2)/(rq/5) 15% for 175 ? rq 350 ? . 4. minimum impedance mode when zq pin is connected to v ddq . 5. operating current is calculated with 50% read cycles and 50% write cycles. 6. standby current is only after all pending read and write burst operations are completed. 7. programmable impedance mode. 8. these are dc test criteria. dc design criteria is v ref 50mv. the ac v ih /v il levels are defined separately for measuring timing parameters. 9. v il (min) dc= - 0.3v, v il (min) ac=-1.5v(pulse width 3ns). 10. v ih (max)dc= v ddq +0.3, v ih (max)ac= v ddq +0.85v(pulse width 3ns). parameter symbol test conditions min max unit note input leakage current i il v dd =max ; v in =v ss to v ddq -2 +2 a output leakage current i ol output disabled, -2 +2 a operating current (x36) : ddr i cc v dd =max , i out =0ma cycle time t khkh min -30 - 550 ma 1,5 -25 - 500 -20 - 450 -16 400 operating current (x18) : ddr i cc v dd =max , i out =0ma cycle time t khkh min -30 - 450 ma 1,5 -25 - 400 -20 - 350 -16 300 standby current(nop): ddr i sb1 device deselected, i out =0ma, f=max, all inputs 0.2v or v dd -0.2v -30 - 230 ma 1,6 -25 - 210 -20 - 190 -16 - 170 output high voltage v oh1 v ddq /2-0.12 v ddq /2+0.12 v 2,7 output low voltage v ol1 v ddq /2-0.12 v ddq /2+0.12 v 3,7 output high voltage v oh2 i oh =-1.0ma v ddq -0.2 v ddq v4 output low voltage v ol2 i ol =1.0ma v ss 0.2 v 4 input low voltage v il -0.3 v ref -0.1 v 8,9 input high voltage v ih v ref +0.1 v ddq +0.3 v 8,10 absolute maximum ratings* *note: 1. stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operat ing sections of this specification is not implied. exposure to absolute ma ximum rating conditions for extended periods may affect reliability. 2. v ddq must not exceed v dd during normal operation. parameter symbol rating unit voltage on v dd supply relative to v ss v dd -0.5 to 2.9 v voltage on v ddq supply relative to v ss v ddq -0.5 to v dd v voltage on input pin relative to v ss v in -0.5 to v dd+ 0.3 v storage temperature t stg -65 to 150 c operating temperature commercial t opr 0 to 70 c industrial t opr -40 to 85 c storage temperature range under bias t bias -10 to 85 c
- 11 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b note: for power-up, v ih v ddq +0.3v and v dd 1.7v and v ddq 1.4v t 200ms v ddq v il v ddq +0.5v 20% t khkh (min) v ss v ih v ss -0.5v 20% t khkh (min) undershoot timing overershoot timing operating conditions (0 c t a 70 c) parameter symbol min max unit supply voltage v dd 1.7 1.9 v v ddq 1.4 1.9 v reference voltage v ref 0.68 0.95 v ground v ss 00v v ddq /2 50 ? sram zo=50 ? 0.75v v ref zq 250 ? ac test output load ac test conditions note : parameters are tested with rq=250 ? parameter symbol value unit core power supply voltage v dd 1.7~1.9 v output power supply voltage v ddq 1.4~1.9 v input high/low level v ih /v il 1.25/0.25 v input reference level v ref 0.75 v input rise/fall time t r /t f 0.3/0.3 ns output timing reference level v ddq /2 v ac electrical characteristics (v dd =1.8v 0.1v, t a =0 c to +70 c) notes: 1. this condition is for ac function test only, not for ac parameter test. 2. to maintain a valid level, the transition edge of the input must: a) sustain a constant slew rate from the current ac level through the target ac level, v il(ac) or v ih(ac) b) reach at least the target ac level c) after the ac target level is reached, continue to maintain at least the target dc level, v il(dc) or v ih(dc) parameter symbol min max unit notes input high voltage v ih (ac) v ref + 0.2 - v 1,2 input low voltage v il (ac) - v ref - 0.2 v 1,2 v ddq +0.25v v ss -0.25v
- 12 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b ac timing characteristics (v dd =1.8v 0.1v, t a =0 c to +70 c) notes : 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control signal are r and w . in case of bw 0 ,bw 1 (bw 2 , bw 3 , also for x36) signal follow the data setup/hold times. 3. if c,c are tied high, k,k become the references for c,c timing parameters. 4. to avoid bus contention, at a given voltage and temperature tchqx 1 is bigger than tchqz. the specs as s hown do not imply bus contention because tchqx 1 is a min parameter that is worst case at totally different test conditions (0 c, 1.9v) than tchqz, which is a max parameter (worst case at 70 c, 1.7v) it is not possible for two srams on the same board to be at such different voltage and temperature. 5. clock phase jitter is the variance fr om clock rising edge to the next expected clock rising edge. 6. vdd slew rate must be less than 0.1v dc pe r 50 ns for dll lock retention. dll lock time begins once vdd and inpu t clock are stable. parameter symbol -30 -25 -20 -16 unit note min max min max min max min max clock clock cycle time (k, k , c, c )t khkh 3.30 8.40 4.00 8.40 5.00 8.40 6.00 8.40 ns clock phase jitter (k, k , c, c )t kc var 0.20 0.20 0.20 0.20 ns 5 clock high time (k, k , c, c )t khkl 1.32 1.60 2.00 2.40 ns clock low time (k, k , c, c )t klkh 1.32 1.60 2.00 2.40 ns clock to clock (k k , c c ) t khk h 1.49 1.80 2.20 2.70 ns clock to data clock (k c , k c ) t khch 0.00 1.45 0.00 1.80 0.00 2.30 0.00 2.80 ns dll lock time (k, c) t kc lock 1024 1024 1024 1024 cycle 6 k static to dll reset t kc reset 30 30 30 30 ns output times c, c high to output valid t chqv 0.45 0.45 0.45 0.50 ns 3 c, c high to output hold t chqx -0.45 -0.45 -0.45 -0.50 ns 3 c, c high to echo clock valid t chcqv 0.45 0.45 0.45 0.50 ns c, c high to echo clock hold t chcqx -0.45 -0.45 -0.45 -0.50 ns cq, cq high to output valid t cqhqv 0.27 0.30 0.35 0.40 ns 7 cq, cq high to output hold t cqhqx -0.27 -0.30 -0.35 -0.40 ns 7 c , high to output high-z t chqz 0.45 0.45 0.45 0.50 ns 3 c , high to output low-z t chqx1 -0.45 -0.45 -0.45 -0.50 ns 3 setup times address valid to k rising edge t avkh 0.40 0.50 0.60 0.70 ns control inputs valid to k rising edge t ivkh 0.40 0.50 0.60 0.70 ns 2 data-in valid to k, k rising edge t dvkh 0.30 0.35 0.40 0.50 ns hold times k rising edge to address hold t khax 0.40 0.50 0.60 0.70 ns k rising edge to control inputs hold t khix 0.40 0.50 0.60 0.70 ns k, k rising edge to data-in hold t khdx 0.30 0.35 0.40 0.50 ns
- 13 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b application information thermal resistance note : junction temperature is a function of on-chip power dissipati on, package thermal impedance, mounting site temperature and mou nting site thermal impedance. t j =t a + p d x ja prmeter symbol typ unit notes junction to ambient ja 17.1 c /w junction to case jc 3.3 c /w pin capacitance note : 1. parameters are tested with rq=250 ? and v ddq =1.5v. 2. periodically sampled and not 100% tested. prmeter symbol testcondition typ max unit notes address control input capacitance c in v in =0v 4 5 pf input and output capacitance c out v out =0v 6 7 pf clock capacitance c clk -56pf sram#1 d sa r w bw 0 q zq k cc sram#4 r vt vt vt r=50 ? vt=v ref vt vt r r=250 ? bw 1 k d sa r w bw 0 q k cc bw 1 k data in data out address r w bw return clk source clk return clk source clk memory controller cq cq zq r=250 ? cq cq zq sram1 input cq sram1 input cq sram4 input cq sram4 input cq
- 14 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b t klkh t khkh t khk h t khkl t avkh t khax a1 a2 t ivkh t khix q1-1 q1-2 q1-3 q1-4 q2-3 t chqx 1 t khch t chqv t chqx t cqhqv t cqhqx t chcqx t chcqv t chqv t chcqx t chcqv t klkh t khkh t khkl t khk h note : 1. q1-1 refers to output from address a1+0, q1-2 refers to out put from address a1+1 i.e. the next internal burst address follow ing a1+0. 2. outputs are disabled one cycle after a nop. k sa r k q c c timing wave forms of read and nop don t care undefined cq cq q2-1 q2-2 d1-1 d1-2 d1-3 d1-4 k sa w k d(data in) timing wave forms of write and nop d2-1 d2-2 t dvkh t khdx don t care undefined note : 1. d1-1 refers to input to address a1+0, d1-2 refers to input to address a1+1, i.e the next internal burst address following a1 +0. 2. bwx (nwx ) assumed active. t klkh t khkh t khk h t khkl t avkh t khax a1 a2 t ivkh t khix d2-3 d2-4 t khix (data out) q2-4 t chqz read nop nop read write nop nop write
- 15 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b a1 a2 timing wave forms of read, write and nop don t care undefined note : 1. if address a3=a2, data q3-1=d2-1, data q3-2=d2-2 , data q3-3=d2-3, data q3-4=d2-4 write data is forwarded immediately as read results. 2.bwx (nwx ) assumed active. k sa w k c c r d(data in) d(data out) a3 d4-3 d4-2 d4-1 d2-4 d2-3 d2-2 d2-1 a4 q3-3 q3-2 q3-1 q1-4 q1-3 q1-2 q1-1 read nop nop read write write
- 16 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b ieee 1149.1 test access port and boundary scan-jtag this part contains an ieee standard 1149.1 compatible test access port (tap). the package pads are monitored by the serial scan circuitry when in test mode. this is to support connectivity testing during manufac turing and system diagnostics. internal data is not driven out of the sram under jtag control. in conformance with ieee 1149.1, the sram contains a tap controller, instruction reg - ister, bypass register and id register. the tap controller has a standard 16-state machine that resets internally upon power-up , therefore, trst signal is not required. it is possible to use th is device without utilizing the tap. to disable the tap control ler without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and ma y be left unconnected. but they may als o be tied to v dd through a resistor. tdo should be left unconnected. tap controller state diagram jtag block diagram test logic reset run test idle 0 11 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. this instruction is not ieee 1149.1 compliant. 2. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 3. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 4. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 5. sample instruction dose not places dqs in hi-z. 6. this instruction is reserved for future use. ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 1 0 0 1 idcode identification register 3 0 1 0 sample-z boundary scan register 2 0 1 1 reserved do not use 6 1 0 0 sample boundary scan register 5 1 0 1 reserved do not use 6 1 1 0 reserved do not use 6 1 1 1 bypass bypass register 4 sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo tdi tms tck cq k,k c,c a,d q cq
- 17 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b id register definition note : part configuration /def=001 for 18mb, /wx=11 for x36, 10 for x18 /t=1 for dll ver., 0 for non-dll ver. /q=1 for qdr, 0 for ddr /b=1 for 4bit burst, 0 for 2bit burst /s=1 for separa te i/o, 0 for common i/o part revision number (31:29) part configuration (28:12) samsung jedec code (11: 1) start bit(0) 512kx36 000 00def0wx0t0q0b0s0 00001001110 1 1mx18 000 00def0wx0t0q0b0s0 00001001110 1 scan register definition part instruction register bypass register id register boundary scan 512kx36 3 bits 1 bit 32 bits 107 bits 1mx18 3 bits 1 bit 32 bits 107 bits note : 1. nc pins are read as ?x? (i.e. don t care.) order pin id 37 10d 38 9e 39 10c 40 11d 41 9c 42 9d 43 11b 44 11c 45 9b 46 10b 47 11a 48 internal 49 9a 50 8b 51 7c 52 6c 53 8a 54 7a 55 7b 56 6b 57 6a 58 5b 59 5a 60 4a 61 5c 62 4b 63 3a 64 1h 65 1a 66 2b 67 3b 68 1c 69 1b 70 3d 71 3c 72 1d order pin id 73 2c 74 3e 75 2d 76 2e 77 1e 78 2f 79 3f 80 1g 81 1f 82 3g 83 2g 84 1j 85 2j 86 3k 87 3j 88 2k 89 1k 90 2l 91 3l 92 1m 93 1l 94 3n 95 3m 96 1n 97 2m 98 3p 99 2n 100 2p 101 1p 102 3r 103 4r 104 4p 105 5p 106 5n 107 5r order pin id 16r 26p 36n 47p 57n 67r 78r 88p 99r 10 11p 11 10p 12 10n 13 9p 14 10m 15 11n 16 9m 17 9n 18 11l 19 11m 20 9l 21 10l 22 11k 23 10k 24 9j 25 9k 26 10j 27 11j 28 11h 29 10g 30 9g 31 11f 32 11g 33 9f 34 10f 35 11e 36 10e boundary scan exit order
- 18 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification . parameter symbol min typ max unit note power supply voltage v dd 1.7 1.8 1.9 v input high level v ih 1.3 - v dd +0.3 v input low level v il -0.3 - 0.5 v output high voltage (i oh =-2ma) v oh 1.4 - v dd v output low voltage(i ol =2ma) v ol v ss -0.4v jtag timing diagram jtag ac charcteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5-ns tms input hold time t chmx 5-ns tdi input setup time t dvch 5-ns tdi input hold time t chdx 5-ns sram input setup time t svch 5-ns sram input hold time t chsx 5-ns clock low to output valid t clqv 010ns jtag ac test conditions note : 1. see sram ac test output load on page 11. parameter symbol min unit note input high/low level v ih /v il 1.8/0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 0.9 v 1 tck tms tdi pi t chch t mvch t chmx t chcl t clch t dvch t chdx t clqv tdo (sram) t svch t chsx
- 19 - rev. 5.0 july 2006 512kx36 & 1mx18 qdr tm ii b4 sram k7r163684b k7r161884b 165 fbga package dimensions side view 13mm x 15mm body, 1.0mm bump pitch, 11x15 ball array bottom view top view symbol value units note symbol value units note a 13 0.1 mm e 1.0 mm b 15 0.1 mm f 14.0 mm c 1.3 0.1 mm g 10.0 mm d 0.35 0.05 mm h 0.5 0.05 mm c f b ? h g a b a d e e

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